The present invention relates to defect management in flash memory devices and, in particular, to an interface controller to such a memory that includes circuitry to reliably track, and prohibit access to, defective sectors.
The use of electrically erasable memory is well-known in the art. For example, standards for xe2x80x9cflashxe2x80x9d memory and circuits for controlling access to the flash memory have been defined by the Personal Computer Memory Card International Association (PCMCIA) and Compact Flash Association (CFA). PCMCIA-compliant cards have been used with portable computers as an adjunct to (or instead of) a hard drive and, more recently, for such devices as digital cameras.
Where an electrically erasable memory can be programmed in one size xe2x80x9cchunkxe2x80x9d, but can only be erased in another (larger) size xe2x80x9cchunkxe2x80x9d, complexity is introduced into the programming operation. For example, with one particular flash memory media, the media can be programmed sector by sector, but can only be erased in segments (which are multiple sectors). Furthermore, where there are manufacturing defects in the memory, which is quite common, this conventionally requires a large amount of overhead to efficiently avoid the defects without also having to disregard a large portion of non-defective memory.
An interface system interfaces a host processor to an electrically-erasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments. A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. The host processor requests access to the memory based on a logical block number.
The interface system includes:
means for using the logical block number to determine from a master index table a physical sector number of a table of physical sector numbers corresponding to the logical block number; and
means for using the logical block number to determine from the table of physical sector numbers the physical sector number on the media corresponding to the logical block number.
With such a system, the memory can be efficiently remapped to address both manufacturing defects and programming considerations.